1. Field of the Invention
This invention relates to circuitry and methods for the synchronization and distribution of clock timing signals within integrated circuits and more particularly to clock timing signal distribution circuitry within integrated circuits such as synchronous dynamic random access memories (SDRAM) that provide an internal clocking signal that has a period that is less than the skewing from the system clocking signals caused by the cumulative delay of the internal clock receiving and distribution circuitry.
2. Description of Related Art
As is well known in the art, an SDRAM has multiple cell arrays within multiple memory banks to retain digital data. The system Address Bus A.sub.0, A.sub.1, . . . , A.sub.n is connected to the Address Buffer to receive the address of the location of the retained digital data within the multiple cell arrays of the multiple memory banks. The Address Buffer transfers the requested address to the appropriate cell array within a selected memory bank, where the row and column address decoders select the appropriate location of the digital data.
The chip select CS, the row address strobe RAS, column address strobe CAS, and the write enable WE signals form a command bus and are received by the command decoder. These signals are decoded and transferred to the control signal generator. The control signal generator generates and transfers a set of control signals that determine the operation modes of the selected cell array in the one memory bank. These modes are variations and combinations of fetching or reading from, storing or writing to, or refreshing of the digital data within the cell arrays of the memory banks.
The data control circuitry receives data from the data input/output buffers which in turn are connected to a system data bus to receive and transmit the digital data DQ.sub.0, . . . , Dq.sub.x to and from the cell arrays within the memory banks.
The external system clock XCLK is transferred to the clock buffer. The clock buffer then transfers the clock to the other operating units of the SDRAM. The clock that controls the timings of the data control circuitry must be such that the digital data DQ.sub.0, . . . , Dq.sub.x is appropriately aligned with the external system lock XCLK.
During periods of inactivity for an SDRAM, it is desirable that the SDRAM be deactivated. This is controlled by a clock enable signal XCKE.
The structure and timing of the clock distribution within the SDRAM is described in "A 2.5 ns Clock Access 250 Mhz, 256 Mb SDRAM with Synchronous Mirror Delay" by T. Saeki et al, IEEE Journal of Solid State Circuits, Vol. 31 No. 11 November 1996, pp. 1656-1664, and shown in FIGS. 1a and 1b. The external system clock XCLK is received by the input buffer IBUF. The input buffer IBUF has a delay time from the input of the external system clock XCLK to the output of the input buffer IBUF that is designated d.sub.1. The output of the input buffer IBUF is the input to multiple internal buffers INTBUF. The internal buffers INTBUF then transfer the internal clock ICLK to the functional units within the SDRAM. The delay time for the internal buffer INTBUF is designated d.sub.2.
The command signals chip select CS, the row address strobe RAS, column address strobe CAS, and the write enable WE, as well as the address bus A.sub.0, A.sub.1, . . . , A.sub.n are gated into the SDRAM during the rise of the internal clock ICLK from a first logic level (0) to a second logic level (1). The internal clock ICLK is the timing signal that is used to synchronize the transfer of the digital data from the cell array in the memory banks to the data input/output buffers and to the data bus DQ.sub.0, . . . , Dq.sub.x. The internal clock ICLK is delayed or skewed by the delay d.sub.1 of the input buffer IBUF plus the internal buffer INTBUF. Since the timing of the functions of the SDRAM are determined by the internal clock ICLK, the access time T.sub.ac of the fetching or reading of the digital data can be no smaller than the clock skew d.sub.1 +d.sub.2 plus the period of the internal clock ICLK. This forces the minimum time that data can be cycled from the SDRAM to be two external system clock XCLK periods. As computer system clocks are approaching transfer rates of 100 Mhz, it is desirable that the access time T.sub.ac of an SDRAM to be brought to one cycle of the external system clock XCLK. This means that the clock skew d.sub.1 +d.sub.2 must be eliminated from the clock distribution system.
Phase Locked Loops (PLL) and Delay Locked Loops (DLL) are well known in the art for synchronizing two timing signals. In both cases, the time to achieve synchronization or lock may be on the order of 50 cycles or more. With such long lock times in SDRAM applications, the internal clocking signals ICLK can not be deactivated during the periods that the SDRAM is inactive. This increases the power dissipation of the SDRAM to undesirable levels.
The Clock Synchronization Delay (CSD) circuits are a class of synchronizing circuits that eliminates the clock skew d.sub.1 +d.sub.2 within two clock cycles. Two types of CSD's known in the art are the latched type CSD and the nonlatched synchronous mirror delay SMD.
FIGS. 2a and 2b show a schematic diagram and a timing diagram for the general structure of a CSD circuit. The external system clock XCLK is received by the input buffer IBUF. The output IBO of the input buffer IBUF is delayed by the delay d.sub.1. The output IBO of the input buffer IBUF is the input to the delay monitor circuit DMC. The delay monitor circuit DMC provides an output that is a delayed input signal IBO by a fixed amount that is usually the sum of the delay d.sub.1 of the input buffer IBUF and the delay d.sub.2 of the internal buffer INTBUF.
The output of the delay monitor circuit DMC is the input of the forward delay array FDA. The forward delay array FDA comprises a number of delay elements that each delay the input of the forward delay array FDA by an increment of time .tau..sub.df. The output of each delay element of the forward delay array FDA is the input for each subsequent delay element and is also one of the multiple outputs of the forward delay array FDA.
The multiple outputs of the forward delay array FDA are inputs to the mirror control circuit MCC. The output IBO of the input buffer circuit IBUF is also provided to multiple inputs of the mirror control circuit MCC. The output IBO of the input buffer circuit IBUF is compared with each output of the forward delay array FDA. When one of the outputs of the forward delay array FDA is aligned with the n+1 pulse of the output IBO of the input buffer IBUF, the mirror control circuit transfers that one output to the backward delay array BDA. The mirror control circuit MCC has multiple outputs to transfer any one of the inputs of the mirror control circuit MCC from the forward delay array FDA to the backward delay array BDA. The backward delay array BDA is comprised of multiple delay elements. Each delay element has a delay time .tau..sub.df equal to the delay time of the forward delay array FDA.
The delayed clock pulse is delayed by a factor of: EQU .tau..sub.FDA =.tau..sub.ck -(d.sub.1 +d.sub.2)
where
.tau..sub.ck is the time of the period of the external clock. PA2 .tau..sub.FDA is the time of the period of the external clock less the skew d.sub.1 +d.sub.2.
The delayed clock pulse is further delayed by the factor .tau..sub.FDA in the backward delay array BDA. Thus, the nth pulse output of the backward delay array BDA is delayed by a factor of EQU 2d.sub.1 +d.sub.2 +2(.tau..sub.ck -d.sub.1 +d.sub.2)
This makes the nth pulse of the backward delay array BDA misaligned with the n+2 pulse of the external system clock XCLK by a factor of the delay d.sub.2 of the internal buffer INTBUF.
The output of the backward delay array BDA is the input of the internal buffer INTBUF. The nth internal clock ICLK is now aligned with the system clock XCLK.
If the system clock XCLK is disabled by a clock enable CLKE and then re-enabled, it requires only two system clock cycles for the internal clock ICLK to align with the system clock XCLK. Thus, any data can be accessed within a single period .tau..sub.ck of the system clock XCLK.
The mirror control circuit MCC is of two types. The first type as described in "Capacitive Coupled Bus with Negative Delay Circuit for High Speed and Low Power (10 GB/s&lt;500 mw) Synchronous DRAM) by T. Yamada et al, Digest of Papers for IEEE Symposium on VLSI Circuits, 1996, pp. 112-113, is a latch that fixes the delay segment of the forward delay element FDA selected to be transferred to the backward delay array BDA. Once the latch is set, it is only reset during the inactivity time of the SDRAM. Upon reactivation of the SDRAM, the decision of the length of the delay necessary is recreated.
The second type of mirror control circuit MCC is the synchronous mirror delay. The mirror control circuit MCC is a pass gate that is activated when the output of the forward delay circuit FDA is aligned with the n+1 pulse of the output IBO of the input buffer circuit IBUF. The synchronous mirror delay chooses on each cycle of the system clock XCLK, which of the delay elements is satisfactory to align with the output IBO of the input buffer circuit IBUF.
As the system timing requirements of modern computers has increased, the frequency of the system clock XCLK has increased to a level such that period .tau..sub.ck of the system clock XCLK may be greater than the clock skew d.sub.1 +d.sub.2. The internal clock can then no longer be guaranteed to synchronized with the system clock XCLK.
U.S. Pat. No. 5,742,194 (Saeki) describes an internal clock generator for a SDRAM. The internal clock generator for the SDRAM provides a phase-advanced internal clock that is stably controlled with an asynchronous clock enabling signal. The asynchronous clock enabling signal provides the control without being detrimental to operation thus providing high-speed operation.
U.S. Pat. No. 5,410,263 (Waizman) teaches an integrated circuit for synthesizing a 50% duty cycle internal clock that is synchronized with zero pulse difference with respect to an external reference clock having a frequency that is equal to, or is a sub-multiple of the synthesized internal Clock. The duty cycle of the synthesized waveform is fixed and invariant with respect to the reference Clock duty cycle. Synchronization of the two clocks is achieved by a delay-line using a voltage controlled delay line with a nominal half period delay of the synthesized clock. The 50% duty cycle is achieved by a second control loop that has as its input both the reference and the inverted synthesized clock. This second loop drives the voltage controlled delay line with the synthesized internal clock signal. The integrated circuit clock synthesizer is intended to operate as an Integral part of a microprocessor or a peripheral unit operating in a system having a common external reference clock.
U.S. Pat. No. 5,923,613 (Tien et. al.) describes a multiple phase latched type synchronized clock circuit. The multiple phase latched type synchronized clock circuit creates a multiple phases of an internal clock signal in an integrated circuit that is synchronized with an external system clock signal is disclosed. A latched type clock synchronizer circuit has an input buffer circuit to receive the external input clock to create a first timing clock. The input buffer is connected to a delay monitor circuit to delay the first timing clock by a first delay factor to create a second timing clock. A delay measurement latch array is connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal, which indicates a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock. A multiple delay array is connected to the input buffer to receive the first timing clock and creates multiple pluralities of incrementally delayed timing clocks. The multiple pluralities of incrementally delay timing clocks and the latched measurement signal are the inputs to a plurality of phase generators that create a plurality of third timing clocks. Each of a plurality of internal buffers is connected to each of the phase generators to receive one of the third timing clocks. The third timing clock is shaped to create one of the multiple phases of the internal clocks which are then buffered, amplified and transmitted to the integrated circuit.